1. Field of the Invention
The present invention relates to information communication. More particularly, the present invention relates to a system and method for packet timing of circuit emulation services over networks.
2. Background Information
Wireless mesh networks are becoming increasingly deployed as multi-service wireless access platforms capable of offering services, such as, for example, WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11n and the like), WiMAX, VoIP, GSM, Edge, CDMA, iDEN, T1 Circuit Emulation Services over Internet Protocol (IP) and other like wireless protocols and standards. In addition to these services, the same wireless mesh networks can be subdivided into “virtual networks” where similar services are carried by competing venders using VLANs or other such techniques.
For reasons of cost effectiveness, the dominant mesh backhaul technologies are generally Time Division Duplexing (TDD) interfaces in which the media is shared between transmit and receive data flows. Such backhaul links can be point-to-point (P2P), point-to-multipoint (P2 MP), or multipoint-to-multipoint (MP2 MP). For WiFi, pre-WiMAX, or WiMAX based backhauls, these mesh networks can rely on an appropriate asynchronous technology to carry packets from one radio in the mesh to another radio in the mesh, in which packets are sent as they are received and the radio channel is available. Other technologies, such as WiMAX, can be synchronous in nature, where specific frame rates, such as, for example, 2.5 milliseconds (ms) or 5 ms frames, are used to transmit data from one WiMAX radio to another. Regardless of the technology and whether the wireless mesh network uses TDD or Frequency Division Duplexing (FDD), packet streams experience many bottle necks where packets must queue when sharing a common wireless media.
Most conventional data services that rely on TCP/IP, UDP, RUDP or other like data flows to carry traffic are designed to be resilient to variations in packet delay and jitter. In contrast, circuit emulation services “tunnel” a time-division multiplexing (TDM) circuit (e.g., T1 or E1) or other like type of circuit through a packet-switched network, thereby using the packet-switched network to emulate the behavior of the TDM circuit. The TDM or other like data is converted into a series of packets for communication through the packet-switched network. The TDM circuit is re-created upon receipt of the data at the destination, such that the TDM equipment on either end of the packet-switched-network are “unaware” that it is connected to anything other than a TDM circuit. However, many circuit emulation services tend to be sensitive to packet jitter. For example, with T1 Circuit Emulation over IP, the packet flows carry data and also carry timing information that is recovered using the packet arrival rate and/or relative packet arrival times. “Packet delay jitter” or, simply, “packet jitter” occurs, because there is some variation in the time each packets takes to reach the destination, even if all of the packets take the same route through the network. More specifically, such circuit emulation services tend to be sensitive to variations in packet jitter caused by other similar data streams or beating with “near” synchronous elements of the network, as well as total general packet loading of the traffic in the wireless mesh network.
Timing recovery can be critical in such circuit emulation services. For example, the source frequency at the entrance to the packet-switched network (referred to as the source clock) must be exactly reproduced at the destination (referred to as the regenerated clock). A difference in frequency between the source and regenerated clocks can result in, over time, a queue at the destination that either fills up or empties, depending on whether the regenerated clock is slower or faster than the source clock. Timing recovery is the process of determining the frequency of the source clock from the varied arrival rates of the packets to establish the regenerated clock.
Many circuit emulation services, such as providing a “traffic T1”, are not sensitive to variations in packet jitter. These services employ algorithms that need only coarsely recover the timing so as to ensure that there are no underflows or overflows and that the timing falls within, for example, the T1 specification of ±32 parts per million as required in ANSI T1.102-1993 (R2005), “Telecommunications—Digital Hierarchy—Electrical Interfaces.” Such a level of timing recovery is modest, requiring only that the buffer receiving the packet flow maintains an average position approximately in the middle of the allocated buffer space.
In contrast, circuit emulation services used for cellular backhaul have very strict timing requirements. Although these circuit emulation services are not required to meet the stringent specifications of a “timing T1” with a Maximum Time Interval Error (MTIE) of 2 μs (3 UI) in 15 minutes, such services are expected to be well-behaved, emulating a timing T1 that is stratum traceable to an absolute frequency. Cellular equipment relies on the absolute accuracy of the received T1 to determine the network timing. For GSM or Edge equipment, the cellular Base Transceiver Stations (BTSs) are required to extract the network timing from the received T1 circuit to within an absolute error of less than 50 parts per billion. Such a functional requirement can have deleterious results if not achieved. For example, if the BTSs in a network exceed an absolute clock accuracy of ±150 parts per billion, then mobility handovers begin to fail. It is therefore imperative that circuit emulation services used for cellular backhaul applications provide stratum-traceable, well-behaved timing.
However, jitter can occur in wired T1. More particularly, jitter can be common and expected in T1 signals. Timing jitter, from clocks or Phase Locked Loops (PLLs), as well as network transients—such as those that result from a Virtual Tributary (VT) where a sudden change in the clock frequency is experienced when the T1 is transported across a Synchronous Optical NETwork (SONET)—experiences a pointer adjustment. Such jitter events are typically of short duration and are generally accounted for by the designers of the BTS timing circuits.
Jitter variation, caused by a change in the fundamental timing statistics of a circuit emulation flow, is inherently non-linear in nature, and, therefore, can be very difficult to filter or eliminate when attempting to achieve accurate absolute clock recovery. A jitter variation, for example, caused by a race condition between two similar frequency packet flows, where the order of arrival of these two flows occasionally reverts across a shared resource or bottleneck within the wireless mesh, can result in periodic changes in packet delay jitter that are on the order of hundreds of microseconds. Consequently, if timing recovery was based on filtering out packet delay variation to achieve a simple PLL, a sudden phase shift in these statistics can be difficult to detect in filtering software. Even more indiscernible are jitter delay variations that appear as a gradual shift in packet delay and occur as competing similar rate packets slowly catch up to each other. These events are dependent upon the relative clock rates of the two data flows.